1. Field of the Invention
The present invention relates to a full flash analog-to-digital (A/D) converter, and more particularly to a full flash A/D converter which can suitably designed as an LSIC (Large Scale Integrated Circuit) and can convert a high-definition television signal of 50 MHz or higher frequencies into a digital signal at high speed.
2. Description of the Prior Art
One conventional flash A/D converter will be described below with reference to FIGS. 1 through 5 of the accompanying drawings.
Japanese Laid-Open Patent Publication No. 62(1987)-32724, for example, discloses a flash A/D converter which can operate at high speed while suppressing digital error.
FIG. 1 schematically shows such a flash A/D converter which includes a reference voltage divider 1 comprising a plurality of series-connected resistors having equal resistances, the resistors being connected between terminals Vra, Vrb to which there are applied voltages that differ from each other by a predetermined potential. The reference voltage divider 1 has 2.sup.n reference potential points VRl through VRx positioned between the resistors and connected respectively to 2.sup.n comparators of a comparator group 2, in which the voltages at the reference potential points VRl through VRx are compared with an analog input signal supplied from an input terminal Vin. The output signal from the comparator group 2 is supplied through an AND gate group 3 to two encoders 4, 5 by which the output signal is converted into a digital signal depending on the level of the analog input signal.
It is assumed that the flash A/D converter is an 8-bit A/D converter. It has 256 comparators divided into four blocks and 256 AND gates divided into four blocks. As shown in FIG. 2A, each of the AND gate blocks 3e through 3t has 64 AND gates A1 through A64. The output signals from comparators C1 through C64 (not shown) are supplied through respective input terminals #1 through #64 to double-phase buffers P1 through P64 which produce two output signals in normal and opposite phases. For example, each AND gate Ai of the second AND gate block 3B is supplied with a normal-phase output signal from a buffer Pi and an on opposite-phase output signal from a buffer Pi+1. The polarities of the input terminals of the comparators are opposite to those shown in FIG. 1. The output signals from the AND gates A1 through A64 are supplied through distribution amplifiers B1 through B64 to wired-OR (WOR) circuits on 7 bit lines SUP, D5 through D0 of a second first-stage encoder block 4B. Each WOR circuit comprises switching transistors, for example, and the WOR circuits are arranged as indicated at "1" in the connection diagram of FIG. 2B.
As shown in FIG. 2A, every four AND gates make up one unit, and D5 through D2 bits of low-order 6 bits of each of the units are shared by four AND gates. The highest-order bit line SUP of the encoder block 4B is supplied with a highest-order-bit output signal from each of three AND gates A1 through A3 and three AND gates A30 through A32 of the first and eighth units 3e, 31 of the second through fourth AND gate blocks 3b through 3h.
Third and fourth encoder blocks 4C, 4D are also of the same construction. In a first encoder block 4A, no WOR circuit is arranged on the line SUP, and each WOR circuit is arranged on the six bit lines D5 though D0. In FIG. 2B, the WOR circuits on the line SUP are indicated at "1*".
FIG. 3 shows another conventional flash A/D converter. As shown in FIG. 3, 6-bit output signals D5 through D0 from the first-stage encoder blocks 4A through 4D are supplied through error inhibiting circuits 6A through 6D each composed of AND gates and inverters, to low-order bit lines D5 through D0 of the second-stage encoder 5, and output signals D5 through D0 from the second through fourth encoder blocks 4B through 4D are supplied to high-order bit lines D7, D6. The high-order bit lines D7, D6 are also supplied with highest-order-bit output signals SUP from the encoder blocks 4B through 4D, generating high-order 2 bits D7, D6.
Output signals SUP, D5 through D0 from the third encoder block 4C (not shown) are supplied to the highest-order bit line D7.
The output signal SUP from the first encoder block 4A is used as an overflow signal. The output signals SUP from the second through fourth encoder blocks 4B through 4D are supplied to the corresponding error inhibiting circuits 6B through 6D and also to the adjacent error inhibiting circuits 6A through 6C.
Output signals from the bit lines D7 through D0 of the encoder 5 are transmitted to respective output terminals through an output inverting circuit 7 which comprises exclusive-OR gates.
In the above conventional flash A/D converter, when an input voltage Vin is applied, the output signals from the first to ith comparators go high, and the output signals from the (i+1)th to last comparators go low, with only the output signal from the ith AND gate at a level changing point being high. The high output signal from the ith AND gate is supplied to the encoders, which then generates a binary code corresponding to the level changing point.
When the slew rate of the input signal Vin is high, since the comparators cannot switch synchronously with the input signal, the H and L levels may have an irregular distribution such as:
. . H H L H* L L L . . .
in the vicinity of the level changing point in the array of the comparators. If a binary code of such an irregular level pattern were supplied to the AND gate group 3, because 2 "H"s are applied to the encoder 4, a very large error (sparkle) would be produced depending on the location where such an irregular pattern occurs. If the error pattern H* is caused between 7F and 80 of a hexadecimal notation, then "FF" will be outputted.
To prevent such an error from taking place, the output signals SUP of the second through fourth encoder blocks 4B through 4D are supplied to the error inhibiting circuits 6A through 6D.
For example, as shown in FIG. 4, in the event an irregular pattern is produced in the vicinity of a point where the D5 bit changes in one AND gate block, and the output signals from the AND gates A31, A32 become H, H*, respectively, the output codes produced by the AND gates A31, A33 are as follows:
______________________________________ D5 D0 ______________________________________ Output code produced by AND gate A31: 011110 Output code produced by AND gate A33: 100000. ______________________________________
The D5 bit is inhibited by the WOR circuits on the line SUP, and the proper output code "011110" is produced, inhibiting an error of 16 LSB or higher. Errors with respect to the low-order 6 bits D4 through D0 are also inhibited.
Furthermore, as shown in FIG. 5, if an irregular pattern is produced between adjacent AND blocks 3A, 3B, and the output signals from the AND gates A63, A1 become H, H*, respectively, then the six low-order bits D5 through D0 of the AND gate block 3A are inhibited. When the irregular pattern does not exceed 32 LSB, the high-order bits D7, D6 are also inhibited.
With the conventional A/D converter, all the output signals from the six low-order bits plus 1 bit are wired-ORed in order to produce two high-order bits. Therefore, the number of sources of the WOR circuits on the high-order bit lines D7, D6 of the second-stage encoder 5 amounts to 16. In the first-stage encoder blocks 4A through 4D, the number of sources of the WOR circuits on the 6 bit lines D5 through D0 also amount to 32. Since the output logic amplitude of the emitters of the WOR circuits is smaller than the input logic amplitude of the bases thereof, a large amplitude is necessary to drive each of the WOR circuits, and the time required to reach a desired amplitude is prolonged.
The load electrostatic capacitance of the highest-order bit line SUP of each of the first-stage encoder blocks 4A through 4D is much greater than that of the other bit lines, it lowers the limit for a delay, i.e., a processing speed.